1. Technical Field
The invention relates to the field of precision electronic resistor circuits.
2. Related Art
During the fabrication of signal processing circuits in a BIMOS or CMOS IC the problem arises of fabricating resistors with sufficient accuracy. Moreover, resistors having high resistance values cannot be realized at low cost on such an IC. Related art circuits are known which generate a resistor by electronic means. For this purpose, use is made, for example, of the source-drain path of a MOS transistor. This path forms an electronically generated and electronically controllable resistance between first and second terminals of the circuit arrangement. The known circuit arrangements have the problem that the resistance generated by the MOS transistor is non-linear, (i.e. the resistance value depends on the voltage applied to the terminals). This is caused by the non-linear drain-source characteristic of a MOS transistor. Moreover, such circuit arrangements have the problem that depending on the drive of the source electrode of the MOS transistor its potential can reach the order of magnitude of the bulk voltage of the MOS transistor. In that case, a diode is formed between the bulk region of the transistor and the source electrode or drain electrode, which gives rise to limiting effects and thus causes distortion of the signal passing through the transistor. Before these effects become active the bulk-source/bulk-drain diode produces a non-linearity which increases with the voltage across the controlled resistance. This effect is known as the xe2x80x9cbackgate effectxe2x80x9d.
It is an object of the invention to provide a circuit arrangement of the type defined in the opening paragraph, which operates with the highest possible degree of linearity and in which the formation of capacitively operating diodes within the bulk region is avoided.
According to the invention this object is achieved is provided apparatus for generating a bulk signal, which apparatus generate from the voltage on the terminal of the circuit arrangement which is coupled to the source electrode of an associated MOS transistor a signal for driving a bulk electrode of the associated MOS transistor. Such signal is generated from the voltage on the terminal and an additionally superposed direct voltage of such a polarity that, depending on the doping type of the MOS transistor, the formation of a diode between the source and bulk regions of this MOS transistor is avoided.
A MOS transistor, as used here for the generation of an electronically controlled resistance, has source and drain electrodes of a first doping type. The gate electrode, by means of which the transistor can be controlled, extends between the source and drain electrodes. The transistor as a whole is formed in a so-called bulk region of a second doping type. In operation transistors of this type have the problem that the source potential should always be smaller than the potential of the bulk zone. If, however, both regions have a similar potential a diode is formed between the source electrode and the bulk region, which diode presents a capacitive and d.c. load to the signal applied to the gate electrode of the transistor, as a result of which the signal is distorted or changed.
In order to avoid this undesired effect and to ensure that the transistor always operates in the most linear region of its drain-source characteristic, in accordance with the invention, apparatus is provided for the generation of a bulk signal which ensures that the conducting diode described above is not formed and that the transistor is operated in a region where its operation is as linear as possible. This is achieved in that the apparatus for the generation of a bulk signal generate this signal in such a manner that the bulk signal includes the superposition of the voltage on that terminal of the circuit arrangement which is coupled to the source electrode of the MOS transistor and an additional direct voltage. Thus, in addition, a direct voltage is superposed on the external signal voltage applied to the source electrode of the transistor. This superposed signal is applied to the bulk electrode of the MOS transistor as the bulk signal. Thus, it is achieved that the potential of the bulk electrode and, consequently, of the bulk region of the transistor is always higher than the potential of the source region of the transistor. This also precludes the effect of the capacitive layer of the diode with respect to the bulk.
The result is that the circuit arrangement thus forms an electronically generated resistance whose value is adjustable by the choice of the gate voltage of the transistor and whose value is highly linear and free from undesired capacitive effects.
With an embodiment of the invention it is achieved that also in the case of an asymmetrical drive of the two terminals the circuit arrangement has the above-mentioned advantages without any restriction.
In accordance with a first more specific embodiment, the apparatus for the generation of the bulk signal or bulk signals can advantageously comprise transistors which are suitable for superposing a direct voltage on the bulk signal of the MOS transistor, which direct voltage is in addition to the source signal, which direct voltage can be generated comparatively simply by a diode junction of the transistor.
Similarly, in a second more specific embodiment, the apparatus for generating the bulk signal include a bipolar PNP transistor having its base coupled to one of the terminals of the circuit arrangement, having its collector coupled to the current source. Also, the MOS transistor is a PMOS transistor, the current source is coupled to a positive supply potential and to the bulk electrode of the PMOS transistor whose source-drain junction is used for the generation of the resistance. Thus, the base-emitter potential difference of a bipolar PNP transistor is used for additionally superposing a d.c. potential on the potential for the generation of the bulk signal, which last-mentioned d.c. potential is coupled to the source region of the MOS transistor.
In a third more specific embodiments the means for generating the bulk signal include a bipolar NPN transistor having its base coupled to one of the terminals of the circuit arrangement, having its collector coupled to a positive supply potential and having its emitter coupled to the current source; and the current source is coupled to a supply potential, and to the bulk electrode of a PMOS transistor whose source-drain junction is used for the generation of the resistance.
Similarly in a second more specific embodiment, the means for generating the bulk signal include a bipolar transistor having its base coupled to one of the terminals of the circuit arrangement, having its collector coupled to a reference potential and having its emitter coupled to the current source. Also, the MOS transistor is a PMOS transistor, the current source is coupled to a positive supply potential and to the bulk electrode of the PMOS transistor whose source-drain junction is used for the generation of the resistance.
In a fourth specific embodiment the means for generating the bulk signal include a PMOS transistor having its gate electrode coupled to one of the terminals of the circuit arrangement, having its drain electrode coupled to a reference potential, and having its source and bulk electrodes coupled to the current source. Also, the current source is coupled to a positive supply potential, and to the bulk electrode of a PMOS transistor whose source-drain junction is used for the generation of the resistance.
In a fifth specific embodiment the means for generating the bulk signal comprise an NMOS transistor having its gate electrode coupled to one of the terminals of the circuit arrangement, having its drain electrode coupled to a positive reference potential and having its source and bulk electrodes coupled to the current source. Also, the current source is coupled to a supply potential, and to the bulk electrode of an NMOS transistor whose source-drain junction is used for generation of the resistance.
These fourth and fifth embodiments use PMOS and NMOS transistors in the apparatus for the generation of the bulk signal. In these transistors the gate-source junction is used for the generation of the potential difference. A requirement for the use of MOS transistors is that the bulk electrodes are free.
In a sixth specific example a resistor is arranged in series with the source dain junctions of at least one MOS transistor whose source-drain junction is used for the generation of the resistance. This has the advantage of a further linearity improvement. The resistors provided therein have comparatively small values. However, they ensure that the resistance values to be generated by means of the transistors can be higher. The resistors of comparatively small resistance value can be fabricated in a relatively simple manner in integrated circuits.